The non-volatile electrically erasable and programmable memory devices—also identified by the acronym EEPROM, “Electrically Erasable Programmable Read Only Memory”—have reached a widespread use in the electronic applications market (from the industrial to the consumer level). Such a wide use is due to special features, such as the ability of retaining information without power supply, allowing the editing of the information thereof, and providing greater reliability than other storage devices, such as magnetic disk storage devices.
The flash memory devices are, currently, the most widespread type of EEPROM devices in that, besides the features above mentioned, they have a very high storage capacity and present at the same time very reduced dimensions.
The memory cells of a flash device may be arranged in a matrix according to a NOR architecture or a NAND architecture. In short, in a NOR architecture the memory cells of the same column of the matrix are connected in parallel to a same column line—or “bit line”—while in a NAND architecture groups of memory cells of the same column of the matrix are connected to each other in series in order to form respective strings, which are then connected in parallel to one another to a same bit line.
The matrix of memory cells of the flash memory devices of the NOR type can be structured according to a column-hierarchy. In this case, the columns of memory cells of the matrix are divided into clusters, each of which consists of a determined number of columns of memory cells. The memory cells of each column are associated with a respective local bit line, while each column cluster is associated with a respective main bit line. During a reading operation, a local bit line for each cluster is selected by selectively coupling it to the corresponding main bit line. In addition, a selected group of main bit lines is selectively coupled to suitable circuitry for the reading of data stored in the memory cells (sense amplifier). Consequently, during a reading operation, each sense amplifier is associated with a corresponding selected local bit line belonging to the selected clusters.
The parasitic capacitances of the local bit lines and of the main bit lines are typically discharged to the ground voltage and then pre-charged to a suitable voltage level before each reading operation. However, the parasitic capacitance of a main bit line has a big entity, since the main bit lines are typically provided with a relatively high length and width, higher than those of the local bit line. Therefore, the time required to discharge and then pre-charge such capacitances is not negligible, and thus increases the overall duration of the reading operation, greatly reducing the performance of the memory device.
During a reading operation, main bit lines are typically pre-charged and discharged in parallel. Given the non-negligible entity of the parasitic capacitances associated with each main bit line, such discharge and pre-charge operations involves as a whole the moving a large amount of charge, implying peaks of power consumption that would result in an effort for the supply circuits of the device, a temperature increase thereof, and above all, electromagnetic emissions that reduce the electromagnetic compatibility of the memory device.
The electronics industry has proposed several solutions to overcome the abovementioned drawbacks. A known technique provides for the reduction of the length of the main bit lines—thereby reducing the capacitance associated with it and the structure of the main bit lines according to a hierarchical solution, where more main bit lines are selectively connectable to a respective global bit line connected to a respective global sense amplifier. Such global bit line will be discharged and pre-charged with different timing than the main bit lines and the local bit lines, thereby distributing the power consumption over time and thus lowering the consumption peak. However, such a solution has a significant cost in terms of area and realization complexity.
A further solution is presented in the article “A 0.13 μm 2.125 MB 23.5 ns Embedded Flash with 2 GB/s Throughput for Automotive Microcontrollers” by Demi, Jankowski and Thalmaier (IEEE, ISSCC 2007, Session 26, Non-Volatile Memories, 26.4) in which is provided to maintain to a pre-charge voltage local bit lines and corresponding reference lines (source line) using an apposite pre-charge circuit. Upon selection, the pre-charge circuit is isolated from the local bit line and the corresponding source line. The source line is connected to a reference terminal, while the local bit line is connected to the sense amplifier through the main bit line. The capacitive coupling between the source line that is discharged and the local bit line causes a small change in voltage on the local bit line that is quickly attenuated by the sense amplifier.
A still further solution is presented in the U.S. Pat. No. 7,236,403 wherein is described a pre-charge arrangement for the reading operation of integrated non-volatile memories having at least one memory cell, at least one source line, at least one bit line, at least one sense amplifier and at least a pre-charge potential. The bit line constantly receives the pre-charge potential in a deselected state of the bit line, and the source line receives a predetermined reference potential, particularly a ground potential, in a selected state of the bit line.